The present invention generally relates to a compression-type power semiconductor device, and particularly relates to a high blocking voltage bipolar power semiconductor device.
FIG. 5 is a sectional view showing a conventional alloy-type gate turn-off thyristor (hereinafter abbreviated to a "GTO") of 5 KV or more, which is disclosed in Japanese Patent Unexamined Publication Nos. Hei-2-248047 and Hei-3-161952. In the drawing, the reference numeral 1 designates an N.sup.- silicon substrate of plane orientation &lt;1,1,1&gt;; 2, a PB layer formed by diffusion of boron by ion-implantation into a front surface of the N.sup.- silicon substrate 1; 3, an NE layer formed by thermal diffusion of phosphorus into the PB layer 2; 4, a PE layer formed by selective ion-implantation of boron into a rear surface of the N.sup.- silicon substrate 1; 5, an N.sup.++ layer formed by thermal diffusion of phosphorus into the outer side of the PE layer; 6, a passivation film of SiO.sub.2 ; 7, an anode electrode; 8, a cathode electrode; 9, a gate electrode; 10, a silicon end surface; 11, passivation rubber made form silicon rubber; and 12 and 13, anode and cathode thermal compensation plates made from molybdenum respectively. The foregoing members constitute a high blocking voltage bipolar semiconductor device.
Description will be made as to a producing method of the foregoing conventional alloy-type GTO. First, boron is ion-implanted into a front surface (cathode side) of the N.sup.- silicon substrate 1 of plane orientation &lt;1,1,1&gt; having a resistivity of 300.about.400 .OMEGA..cm and a thickness of 700 .mu.m or more, and then drive-in diffused by heat treatment at 1250.degree. C. for about 170 hours, resulting in formation of the PB layer 2 having a surface boron concentration of 10.sup.17 .about.10.sup.18 atoms/cm.sup.2 in the depth of 80.about.90 .mu.m.
Next, phosphorous is deposited onto the PB layer 2 and heat-treated at 1250.degree. C. for about 8 hours so as to be drive-in diffused, resulting in formation of the NE layer 3 having a surface phosphorous concentration of 10.sup.19 .about.10.sup.20 atoms/cm.sup.2 in the depth of 20.about.25 .mu.m.
Next, boron is selectively ion-implanted onto a rear surface (anode side) of the N.sup.- silicon substrate and heat-treated at 1250.degree. C. for about 2 hours so as to be drive-in diffused, resulting in formation of the PE layer 4 having a surface boron concentration of 10.sup.18 .about.10.sup.19 atoms/cm.sup.2 in the depth of 10.about.12 .mu.m.
Next, phosphorous is selectively deposited onto the anode side and heat-treated at 1250.degree. C. for about 1 hour so as to be drive-in diffused, resulting in formation of the N.sup.++ layer 5 having a surface phosphorous concentration of 10.sup.19 .about.10.sup.20 atoms/cm.sup.2 in the depth of 5.about.10 .mu.m.
Next, aluminum is evaporated onto the anode side to thereby form the anode electrode 7, and aluminum is evaporated onto the surface of the anode thermal compensation plate 12. Then, the aluminum-evaporated surface of the anode thermal compensation plate 12 and the anode electrode 7 are heated so that they are made of the alloy-type. Further, after the cathode and gate electrodes 8 and 9 each having a thickness of about 10 .mu.m are formed on the cathode side by aluminum evaporation, sputtering, or the like, they are heat-treated at 400.degree..about.500.degree. C. for 30.about.60 minutes so as to improve the ohmic contact.
There is provided a stage portion of about 30 .mu.m between the cathode and gate electrodes 8 and 9, and the junction portion at the stage portion between the NE and PB layers 3 and 2 is covered with the passivation film 6 such as an SiO.sub.2 film, or the like, so as to be protected from contamination of sodium, or the like. Further, the end surface of the silicon substrate 1 is shaped into a positive bevel so as to relieve the electric field intensity, the silicon end surface 10 is covered with the passivation rubber 11 of silicon rubber, and the cathode thermal compensation plate 13 is pressed against the silicon substrate 1 on its cathode side to thereby complete the GTO of FIG. 5.
As described above, in the conventional GTO, the silicon substrate 1 of crystal orientation &lt;1,1,1&gt; was used. The reason why the silicon substrate 1 of crystal orientation &lt;1,1,1&gt; is used is that the mechanical strength thereof is large against stress such as thermal strain, or the like, generated in formation of an alloy-type junction so that crack is hardly generated in the producing process.
In the compression-type semiconductor device having such a conventional configuration, however, there has been a problem that a leak current upon voltage application increases to reduce the blocking voltage yield.
Further, a long time is required for heat treatment for drive-in diffusion, and, therefore, shortening of the production term as well as reduction of the cost have been required.